System information

FCD 901 48
Issue R2A, 07.2009
XMP1 Release 5.5 System Description
Frame structure
Aastra Proprietary Information Page 2-5
Frame
Frame alignment signal
The frame alignment signal required for synchronization is transmitted in
time slot 0 of every other frame.
Bit X in position 1 is used for transmitting the CRC4 bits.
If the CRC4 procedure is not applied, bit X is set to logic 1.
The bits in positions 2 to 8 define the binary values of the synchronization
pattern.
Table 2.A: Frame alignment signal
Bit position 12345678
Binary valueX0011011
Channel no.
Time slot
Signalling informationFrame alignment signal
8 bit / 3.9s
30 31 0 1
29 30 1
15 16 17 18
Pulse frame
Multiframe structure
256 bit / 125s
Channel information
256 bit / 125s
Service digits
x1 NYY YD
iiiiiiii
16
Time slot 16
Frame 14 Frame 15 Frame 1 Frame 3 Frame 2 Frame 0
2 ms
125s
a b c d a b c d
0 0 0 0 1 0 1 1
a b c d a b c d
2930 1234
303101234
X00 011 11 abcdabcd
15 1617
15 16 1718
29 30
30 31 0 1 2
Signalling
15 3116 1712
Figure 2.2: Frame structure
Frame alignm. signal for
Voice channel 15 Voice channel 30
Frame alignm. signal for
Voice channel 1
Voice channel 16
Multiframe
service
digits
Multiframe
alignment
signal
16
16
16
16
information
Y