System information

FCD 901 48
Issue R2A, 07.2009
XMP1 Release 5.5 System Description
Functioning
Aastra Proprietary Information Page 2-1
Chapter 2
Functioning
The XMP1 Flexible Multiplexer digitizes and multiplexes both voice and
data information from subscribers. The data are transmitted to the XMP1
network and can be read, demultiplexed and sent again to the subscribers
in each XMP1 node.
2.1 General Functions
Transmit direction
In the transmit direction, the voice information to be transmitted is digitized.
In doing so, it is subjected to a quantization and transmitted as 8 bit word
via the system data bus at 2 Mbit/s.
The system data bus is a 32 Mbit/s data bus. It is 8 bit wide and divided into
512 time slots.
The entire information of the system data bus is available at each module.
The information as to when a module can extract the 64 kbit/s data from or
insert them into the system data bus is contained in the allocation memories
of the individual modules.
The channel module transmits the 64 kbit/s data in the time slot assigned to
it on the system data bus.
The port module now extracts the 64 kbit/s data of the channel module from
the system bus and sends them to the multiplexer.
In the transmit direction, the multiplexer on the port module combines 30
digital signals of 64 kbit/s each + 2 kbit/s or 31 x 64 kbit/s digital signals to
one 2.048 Mbit/s signal.
The digital signals are multiplexed in the allocated time slots defined by the
PCM frame structure. The allocation between time slots and 64 kbit/s
signals is freely selectable.
For synchronizing the demultiplexer of the opposite station, a frame
alignment signal is inserted in the bit stream.
The F1 interface performs the conversion to the line code and matches the
signals with the transmission medium used.
The F1 interface can be designed as
• HDB3 code equipment interface (Port (2), (4))
• line interface for copper cables (LE port) or
• line interface for optical fiber cables (LE2 OPT U port).
Receive direction
In the receive direction, the 2 Mbit/s signal received at F1in is regenerated
on the port module. The receive signal is used to recover the 2 MHz receive
clock and the receive code is converted again into its binary form. The