System information

FCD 901 48
Issue R2A, 07.2009
XMP1 Release 5.5 System Description
Abbreviations
Aastra Proprietary Information Page xxv
FCD 901 48
Issue R2A, 07.2009
PeC Persistance Check
PLL Phase Locked Loop
Px Port x, x = no.
Q Acknowledgement
QuP Source Port
RAM Random Access Memory
REP Repeater
RF Radio Frequency
RKW Frame Alignment Signal
S Card Protection Switching
SD System Bus
Si and SiII Signalling Bits for Multiframe Sections
SOX ServiceOn XMP1, Element Manager
STRV Power Supply
SUB Subscriber
Subscr. no. Subscriber No.
SYN Synchronization
T3in External Clock T3, 2048 kHz, input
T3out External Clock T3, 2048 kHz, output
T8M 8.192 MHz Clock
T8V 8.192 MHz Clock, 90° phase-shifted with respect to T8M
TCP/IP Transmission Control Protocol/Internet Protocol
TF Carrier Frequency
TG Trunk Group
TINT Internal Clock
TS Time Slot
V Preferred Direction
W 19" Subrack
WT VF Telegraphy
XMP1 Cross-Connect Multiplexer, plesiochronous, 1st hierarchy
ZE Central Unit Firmware without card firmware
zFa Central Unit Firmware, active
zFp Central Unit Firmware, passive
ZG Central Unit Firmware, complete
ZNK Central Network Node
Table 0.A: Abreviations
ABBREVIATION MEANING