System information

FCD 901 48
Issue R2A, 07.2009
XMP1 Release 5.5 System Description
Clock
Aastra Proprietary Information Page 5-11
5.5 Clock
The SHDSL extension uses the SHDSL clock mode 1 (plesiochronous).
Internal 2 Mbit/s interfaces
The internal 2 Mbit/s interfaces are synchronized using the XMP1 system
clock.
External 2 Mbit/s interfaces
Using the external 2 Mbit/s interfaces, the clock of the external 2 Mbit/s
signal or the XMP1 system clock can be used. The appropriate setting is
made via the operator software.
Recovered
E1 clock
System
clock
SDSL
NT
FALC
E1
framer
PSP E
SDSL
LT
FALC
E1
framer
PSPE
Recovered
SDSL clock
System
clock
S ign al
clock
Sig nal
clock
Integrated
ope ratio n
Recovered
E1 clock
SDSL
NT
FALC
E1
framer
SDSL
LT
FALC
E1
framer
Recovered
SDSL clockStand-alone
operation