System information

FCD 901 48
Issue R2A, 07.2009
XMP1 Release 5.5 System Description
E1 interface
Page 5-8 Proprietary Information Aastra
5.3.2 E1 interface
The ISHDSL module provides four external E1 interfaces and four internal
E1 interfaces to the XMP1 kernel.
If the SDSL line equipment is used as stand-alone system, only the external
E1 interfaces are used. The E1 signal is passed on transparently to the
SHDSL interface without CAS termination.
The E1 interface complies with the classical ITU-T G.703/G.704
recommendations. In case of a full 2048 kbit/s transmission bandwidth, the
user can select between structured operation (G.704) and transparent
operation.
A reduced bandwidth results in a structured E1 fractional mode. Time slots
not transmitted will be filled with an AIS signal on the E1 side.
Transparent mode
The transparent mode is used for transmitting any E1 signals. The E1 signal
requires no frame structure. In case of a signal failure, AIS will be injected.
This operating mode does not permit E1 performance data evaluation.
Structured mode (G.704)
For this operating mode, the E1 signal must have a PCM30/31 frame
structure. The evaluation of the frame alignment signal, CRC4 frame and E
bits permits the display of E1 performance data. Depending on the
application, time slot 0 (TS0) processing can be configured in different
ways.
Adjustable TS0 modes:
• Transparent through-connection
• Terminating operation without CRC4
• Terminating operation with CRC4
• XMP1 frame alignment signalling (always with CRC4)