System information

FCD 901 48
Issue R2A, 07.2009
XMP1 Release 5.5 System Description
Clock Management
Aastra Proprietary Information Page 3-27
• Test loop (port, switching matrix)
STM-1/4 Regenerator Section
• Trail trace identifier
• BER thresholds
• Switch through byte D, E, F
STM-1/4 Multiplex Section
• BER thresholds
• Switch through byte D, E
• Forced SSM
Higher Order Path
• Signal structure, signal label
• Trail trace identifier
• BER thresholds
2Mbit/s interfaces
• Interface modes (PCS, transparent)
• Retiming mode
Lower Order Path
• Mapping
• Signal label
• Trail trace identifier
• BER thresholds
3.8.2.3 Clock Management
The Clock Management deals with the configuration and behaviour of
SETG functions. Its main tasks include:
• Configuration of timing sources (T1, T2, T3, internal oscillator)
• Quality of timing sources
• Priority of timing sources
• Clock selection criteria (quality, priority, error status)
For further information, please refer to Section 3.6, Clock Supply .
3.8.3 Software and Data Management
Application software
The application software of the SDH expansion running on the SCU module
and CU-E sub-module must be considered separate from the XMP1 Central
Unit software. It is stored in a FLASH memory on the CU-E sub-module.