System information

FCD 901 48
Issue R2A, 07.2009
XMP1 Release 5.5 System Description
Clocks T3 and T4
Aastra Proprietary Information Page 3-15
If you want the clock network of the PDH network to remain independent,
do not select the "Use SDH clock" setting. The PDH clock selection will then
be independent of the SDH system clock T0. In this case, the current status
of PDH clock selection will not be visible in the SOA.
Since the T3 and T4 status of the XMP1 PDH section is not visible in the
SOA, it is necessary for an XMP1 with SDH expansion to relocate the
external clocks T3 and T4 from the Central Unit to the SCU. This also
improves the clock quality, because the PLLs of the SDH expansion provide
a higher quality. In this case, the clock lines must be connected to X22 of
the SCU module.
3.6.5 Clocks T3 and T4
The timing interfaces T3 and T4 are implemented on the 9-pin Sub-D
connector X22 (male). This connector is located on the front side of the SCU
module.
The impedance of the T3 interface can be set to highly resistive
(>1.6 kOhms), 120 Ohms or 75 Ohms.
SETG
function
NMS view
T2
T1
T3
T0
T4
PET
function
64k T4
64k T0
64k T2
64k T3
Setting:
Use SDH clock