System information
FCD 901 48
Issue R2A, 07.2009
XMP1 Release 5.5 System Description
Clock Supply
Aastra Proprietary Information Page 3-11
3.6 Clock Supply
For their internal switching process, the network elements included in an
SDH network require a highly precise and stable clock (2048 kHz) which
must be recovered from a reference timing source (Primary Reference
Clock PRC).
The SDH expansion in the XMP1 system provides a SETS functionality
according to EN 300 417-6-1 (Synchronization Layer).
The SDH expansion can recover its clock from one of the following
reference timing sources:
• the clock of an STM-N signal received (T1: STM-N port, SCU module),
• the clock of a 2 Mbit/s signal received (T2: plesiochronous port, SCU
module, ext. 2 Mbit/s interface),
• the synchronous network clock signal applied to the T3 interface,
• the internal clock generated by a local oscillator.
Figure 3.5: Synchronous Equipment Timing SETG
Irrespective of the clock quality, clock selection can take place using the
associated priorities in both the revertive and non-revertive mode. The
STM-1 line interfaces are supporting the SSM functionality.
A retiming function is possible for external 2 Mbit/s signals.
SETG
function
T1
T3
T0
T4
SCU
T2
STM-N port
Plesiochr. port