Installation guide

Half-size SBC HSB-910I

Appendix A Programming the Watchdog Timer A-4

Bit Description

7-2 Reserved

1 Returns to the Wait for Key state. This bit is used when the

configuration sequence is completed.

0 Resets all logical devices and restores configuration registers

to their power-on states.

WatchDog Timer Control Register (Index=71h, Default=00h)

Bit Description

7 WDT is reset upon a CIR interrupt

6 WDT is reset upon a KBC (Mouse) interrupt

5 WDT is reset upon a KBC (Keyboard) interrupt

4 WDT is reset upon a read or a write to the Game port base

address

3-2 Reserved

1 Force Time-out. This bit is self-clearing

0 WDT status

1: WDT value reaches 0

0: WDT value is not 0

WatchDog Timer Configuration Register (Index=72h,

Default=00h)

Bit Description

7 WDT Time-out value select

1: Second

0: Minute

6 WDT output through KRST (pulse) enable

5 WDT Time-out value Extra select

1: 4s.

0: Determine by WDT Time-out value select (bit7 of this

4 WDT output through PWROK1/PWROK2 (pulse) enable

3 Select the interrupt level

note

for WDT