Instruction manual

Chapter 3 Award BIOS Setup 65
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at
C0000h to C7FFFh, resulting in better video performance. However,
if any program writes to this memory area, a system error may
result.
Video RAM Cacheable
Selecting Enabled allows caching of the video memory (RAM) at
A0000h to AFFFFh, resulting in better video performance. Howev-
er, if any program writes to this memory area, a memory access error
may result.
8/16 Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles between PCI-
originated I/O cycles to the ISA bus. This delay takes place
because the PCI bus is so much faster than the ISA bus.
These two fields let you add recovery time (in bus clock cycles) for
16-bit and 8-bit I/O.
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter ROM.
When this area is reserved, it cannot be cached. The user informa-
tion of peripherals that need to use this area of system memory
usually discusses their memory requirements.
Passive Release
When Enabled, CPU to PCI bus accesses are allowed during
passive release. Otherwise, the arbiter only accepts another PCI
master access to local DRAM.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance
with PCI specification version 2.1.